The present invention generally relates to semiconductor devices structures, and particularly to the fabrication of self-aligned gate electrode diffusion barriers.
In complementary metal-oxide semiconductor (CMOS) technology, an n-type field-effect transistor (nFET) and a p-type field effect transistor (pFET) may be paired together. As CMOS technology continues to shrink, the space between the nFET and the pFET may also continue to shrink. One technique to reduce the space required of an nFET/pFET pair is to have both transistors share a common gate. For example, referring to FIG. 1, a CMOS device 10 may include an nFET 11 and a pFET 12 formed on a semiconductor substrate 13. The nFET 11 may include nFET source/drains 14, while the pFET 12 may include pFET source/drains 15. The nFET 11 and the pFET 12 may share a common gate 16.
In part to allow for a decreased thickness of the gate dielectric layers, the gates of pFETs and nFETs may be doped with p-type and n-type dopants. For instance, the common gate 16 may include an n-doped portion 17 for the nFET 11 and a p-doped portion 18 for the pFET 12. However, as depicted in FIG. 2, it may be possible for dopants to diffuse from the p-doped portion 18 to the n-doped portion 17, or vice versa, particularly during periods of high temperature. Should the dopants diffuse too far toward either the opposite device, the CMOS device 10 may suffer from reduced performance or fail to operate entirely. Therefore a method of preventing dopant diffusion between the nFET portion and the pFET portion of a shared common gate of a CMOS device may be, among other things, desirable.